Is it a good idea to use uvm_event_pool to broadcast reset assertion/de-assertion information across the UVM testbench components (rather than passing through vif)? Would like to trigger a stimuli from sequence, after reset assertion which may be triggered from other random sequences (would like to avoid vif access in sequence, obviously)
Will this cause any chaos as uvm_event_pool is not well protected and can be modified (triggered) from anywhere?
In reply to sanoopvl:
Reset (and clock) signals should be part of your interfaces, and not passed through the UVM hierarchy. The reason for this is that each interface may use a separate reset (and clock), so you want your agent driver/monitor to be cognizant of it’s associated reset.
Stimulus generation should have no dependency on any reset. It is only when the sequence_item reaches the driver that the reset signal is considered. Your first set of sequence_items should occur at time 0.
In reply to cgales:
Thanks for the reply. Sorry I missed out an important detail in my original post. It is a soft reset. Triggered by a register write.