Hi I want to pass a memory register instance to a class (extended from uvm_object) from my testcase (extended from base_test, again which is extended from uvm_test).
In my test :
class my_test extends base_test;
//...
cci_prog_parameters cci_prog;
virtual function build_phase(uvm_phase phase);
super.build_phase(phase);
cci_prog = new("cci_prog",mem_reg); // passing the memory register from testcase
uvm_config_db#(cci_prog_parameters)::set(this,"env.*", "cci_prog", cci_prog);
cci_prog.set_cci_clk();
//... display statement to read cci_prog.cci_clk_freq.
//...other codes and a display statement to check whether reading from memory is successful or not
endfunction
endclass
class cci_prog_parameters extends uvm_object;
reg [7:0] local_mem [0:255]
real cci_clk_freq;
function set_cci_clk();
bit [7:0] cci_clk = local_mem[0];
this.cci_clk_freq = cci_clk[7:0];
endfunction
function new(string name = "", reg [7:0] mem_reg [0:255]);
super.new(name);
this.local_mem = mem_reg;
endfunction: new
endclass
I don’t think this will work, because of UVM hierarchy. In my simulator i am facing some other issue that’s why could not get the output for the above code.
Can anyone please give me a solution to this. I will attach the output as soon as I resolve my simulator issue.
If binding for that mem_reg can be done, then please help me with that also.
Thanks,
Biren