Assertion is used in the DUT and binded with testbench.But why the simulation not showing any PASS of FAIL response

UVM
1 
//DUT with Assertion
module dut(clk, req, gnt);
input logic clk,req;
output logic gnt;
  always_ff@(posedge clk)begin 
    if(req)
      gnt<=0;
    else 
      gnt<=1;
  end 
endmodule

//TestBench 
module dut_property(pclk,preq,pgnt);
input pclk, preq, pgnt;
`ifdef no_implication
property pr1;
@ (posedge pclk) preq ##2 pgnt;
endproperty
preqGnt: assert property (pr1) $display($stime,,,"\t\t %m PASS");
else $display($stime,,,"\t\t %m FAIL");
`elsif implication
property pr1;
@ (posedge pclk) preq |-> ##2 pgnt;
endproperty
preqGnt: assert property (pr1) $display($stime,,,"\t\t %m PASS");
else $display($stime,,,"\t\t %m FAIL");
`elsif implication_novac
property pr1;
@ (posedge pclk) preq |-> ##2 pgnt;
endproperty
preqGnt: assert property (pr1) else $display($stime,,,"\t\t %m FAIL");
property pr2;
@ (posedge pclk) preq ##2 pgnt;
endproperty
cpreqGnt: cover property (pr2) $display($stime,,,"\t\t %m PASS");
`endif
endmodule



//Binding the DUT and property
`define no_implication
module test_dut;
bit sys_clk,sys_req;
wire sys_gnt;
/* Instantiate 'dut' */
dut dut1 (
.clk(sys_clk),
.req(sys_req),
.gnt(sys_gnt)
);
  bind dut1 dut_property dpM(.pclk(clk),.preq(req),.pgnt(gnt)) ;
  always @ (posedge sys_clk)
$display($stime,,,"clk=%b req=%b gnt=%b",sys_clk,sys_req,sys_gnt);
always #10 sys_clk = !sys_clk;
initial
begin
sys_req = 1'b0;
@ (posedge sys_clk) sys_req = 1'b1; //30
@ (posedge sys_clk) sys_req = 1'b0; //50
@ (posedge sys_clk) sys_req = 1'b0; //70
@ (posedge sys_clk) sys_req = 1'b1; //90
@ (posedge sys_clk) sys_req = 1'b0; //110
@ (posedge sys_clk) sys_req = 1'b0; //130
@ (posedge sys_clk);
@ (posedge sys_clk); $finish(2);
end
endmodule
2

In reply to designMaster:

Please use code tags to make your code more readable. I have added them for you.

Also, which `defines were used to simulate?

3

In reply to dave_59:

ok its done thanks.

4

In reply to designMaster:

If you compiled your code exactly as show, There are NO defines when the module dut_property gets compiled.