Hello,
https://verificationacademy.com/forums/systemverilog/creating-array-sequences
I referred to this post to understand how to create an array of sequences. I’d like some further clarifications.
I have a wreq seq, wdata seq and a top write seq (that forks of the 2 sequences in parallel, so they start at the same clk).
In my case, the wdata seq depends on some rand variables inside wreq_seq. I would like to simulate a case where multiple wreq sequences are issued before the 1st wdata seq.
Assuming I create an array of wreq sequences, how can I make a “wreq/wdata” pair before starting them ?
In words:
- make an array of wreq sequences
- make an array of wdata sequences, each wdata_seq should be formed by taking the random variables inside wreq seq into consideration.
- send multiple wreq sequences, followed by wdata sequences.
Please let me know your suggestions.