Accessing successive numbered registers in SV/UVM

UVM
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1

Hi,
I am looking to access numbered registers: reg0, reg1, reg2,… and stat0,stat1,stat2,… but the number of registers that I access is dependent on a variable n
For Eg: n=1 =>
reg_blk.reg0.write(status,value0);
reg_blk.stat0.write(status,valstat0);

n=2 =>
reg_blk.reg0.write(status,value0);
reg_blk.stat0.write(status,valstat0);
reg_blk.reg1.write(status,value1);
reg_blk.stat1.write(status,valstat1);

and so on…

Is there any way of doing this?

Thank You