Zero Period Glitch detection

UVM
, ,
1

Hi,

I am trying to write a glitch checker(in the form of a system verilog task) on clocks. The glitch checker is able to detect the zero time glitches but it is not able to detect zero period glitches (when I say zero period glitch it means that 3 of the clock edges are happening at the same time). I tried couple of things in coming up with a solution for the above problem but in vain. I am trying to approach a problem based on scheduling semantics in system verilog but no successful results as of now. Has anyone on this forum faced a similar problem before? Or is there a solution possible to above problem considering the scheduling semantics of system verilog?

Hoping for a positive reply.

Thanks !!

2

There is no way to do this predictably in SystemVerilog because there is no deterministic ordering of events withing the same time slot. And there is no such thing as a zero delay glitch in hardware - it is an artifact of event driven simulation and usually caused by improper modeling.

There are tools that will help you either find theses improperly coded designs, or record the zero-delay glitch that you can search for while debugging.