Xmsim: *E,ASRTST assertion failed

SystemVerilog
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1

I am trying to assert this property:

assert_1:
    assert property ( @(posedge clk) disable iff (!a)
              (b == 1'b0) |-> (c == 1'b1) )
        `uvm_error("ASSERT", "c cannot go high")
    else `uvm_info("ASSERT", "c should be in high state after b bit is set",UVM_LOW)

What is wrong with this? and what does the following error mean?

xmsim: *E,ASRTST (…/bench/top/assertions.sv,204): (time 1500 NS) Assertion top.assertions.assert_1 has failed (2 cycles, starting 500 NS) 1500 NS + 3 (Assertion output stop: top.assertions.assert_1 = failed)

2

You have the pass and fail action blocks reversed.
assert property(prop) pass_action_block else
Fail_action_block;
Ben