In reply to dave_59:
Hi Dave,
Thank you for your input.
I added this
package ams_signal_pack_sv;
typedef struct {
real amplitude;
real frequency;
real phase;
} signal_rf;
endpackage
//end ams_signal_pack_sv
and included it in my code
module rxbb_lp_model_wrapper
// import analog_pack_sv::*;
// import analog_model_ctrx_pack_sv::*;
// import ams_signal_pack_sv::*;
import ams_signal_pack_sv ::*;
(
VDD1V8BB ,
VSS1V8A ,
VSS1V8BB ,
VSS_SUB ,
bbmux_lp_n_ai_amplitude ,
bbmux_lp_n_ai_frequency ,
bbmux_lp_n_ai_phase ,
bbmux_lp_p_ai_amplitude ,
bbmux_lp_p_ai_frequency ,
bbmux_lp_p_ai_phase ,
lp_n_ai_amplitude ,
lp_n_ai_frequency ,
lp_n_ai_phase ,
lp_p_ai_amplitude ,
lp_p_ai_frequency ,
lp_p_ai_phase ,
ibg_lp_untrim_50u_p_ai ,
iptat_lp_untrim_50u_p_ai ,
lp_en_i ,
lp_noise_filter_en_i ,
lp_test_sel_i ,
trim_lp_fb_fc_i ,
trim_lp_pass_fc_i ,
vcm1_750m_ai ,
vcm3_600m_ai ,
lp1_n_amux_ao,
lp1_p_amux_ao,
lp2_n_amux_ao,
lp2_p_amux_ao,
lp_n_ao,
lp_p_ao
);
input analog_t VDD1V8BB;
input analog_t VSS1V8A;
input analog_t VSS1V8BB;
input analog_t VSS_SUB;
input analog_t bbmux_lp_n_ai_amplitude ;
input analog_t bbmux_lp_n_ai_frequency ;
input analog_t bbmux_lp_n_ai_phase ;
input analog_t bbmux_lp_p_ai_amplitude ;
input analog_t bbmux_lp_p_ai_frequency ;
input analog_t bbmux_lp_p_ai_phase ;
input analog_t lp_n_ai_amplitude ;
input analog_t lp_n_ai_frequency ;
input analog_t lp_n_ai_phase ;
input analog_t lp_p_ai_amplitude ;
input analog_t lp_p_ai_frequency ;
input analog_t lp_p_ai_phase ;
input analog_t ibg_lp_untrim_50u_p_ai [1:0];
input analog_t iptat_lp_untrim_50u_p_ai [1:0];
input logic lp_en_i;
input logic lp_noise_filter_en_i;
input logic lp_test_sel_i;
input logic [2:0] trim_lp_fb_fc_i;
input logic [3:0] trim_lp_pass_fc_i;
input analog_t vcm1_750m_ai;
input analog_t vcm3_600m_ai;
output analog_t lp1_n_amux_ao;
output analog_t lp1_p_amux_ao;
output analog_t lp2_n_amux_ao;
output analog_t lp2_p_amux_ao;
output analog_t lp_n_ao;
output analog_t lp_p_ao;
signal_rf bbmux_lp_p_ai;
signal_rf bbmux_lp_n_ai;
signal_rf lp_p_ai;
signal_rf lp_n_ai;
initial
begin
bbmux_lp_n_ai.amplitude = bbmux_lp_n_ai_amplitude;
bbmux_lp_n_ai.frequency = bbmux_lp_n_ai_frequency;
bbmux_lp_n_ai.phase = bbmux_lp_n_ai_phase;
bbmux_lp_p_ai.amplitude = bbmux_lp_p_ai_amplitude;
bbmux_lp_p_ai.frequency = bbmux_lp_p_ai_frequency;
bbmux_lp_p_ai.phase = bbmux_lp_p_ai_phase;
lp_n_ai.amplitude = lp_n_ai_amplitude;
lp_n_ai.frequency = lp_n_ai_frequency;
lp_n_ai.phase = lp_n_ai_phase;
lp_p_ai.amplitude = lp_p_ai_amplitude;
lp_p_ai.frequency = lp_p_ai_frequency;
lp_p_ai.phase = lp_p_ai_phase;
end
// Instantiate the system_verilog model
rxbb_lp_model rxbb_lp_model_inst(
.VDD1V8BB(VDD1V8BB) ,
.VSS1V8A(VSS1V8A) ,
.VSS1V8BB(VSS1V8BB) ,
.VSS_SUB(VSS_SUB) ,
.bbmux_lp_n_ai(bbmux_lp_n_ai) ,
.bbmux_lp_p_ai(bbmux_lp_p_ai) ,
.ibg_lp_untrim_50u_p_ai(ibg_lp_untrim_50u_p_ai) ,
.iptat_lp_untrim_50u_p_ai(iptat_lp_untrim_50u_p_ai) ,
.lp_en_i(lp_en_i) ,
.lp_n_ai(lp_n_ai) ,
.lp_noise_filter_en_i(lp_noise_filter_en_i) ,
.lp_p_ai(lp_p_ai) ,
.lp_test_sel_i(lp_test_sel_i) ,
.trim_lp_fb_fc_i(trim_lp_fb_fc_i) ,
.trim_lp_pass_fc_i(trim_lp_pass_fc_i) ,
.vcm1_750m_ai(vcm1_750m_ai) ,
.vcm3_600m_ai(vcm3_600m_ai) ,
.lp1_n_amux_ao(lp1_n_amux_ao) ,
.lp1_p_amux_ao(lp1_p_amux_ao) ,
.lp2_n_amux_ao(lp2_n_amux_ao) ,
.lp2_p_amux_ao(lp2_p_amux_ao) ,
.lp_n_ao(lp_n_ao) ,
.lp_p_ao(lp_p_ao)
);
endmodule
module rxbb_lp_model
//import analog_pack_sv::*;
//import analog_model_ctrx_pack_sv::*;
//import ams_signal_pack_sv::*;
import ams_signal_pack_sv ::*;
#(parameter time sample_rate=1ns) ( lp1_n_amux_ao, lp1_p_amux_ao, lp2_n_amux_ao, lp2_p_amux_ao,
lp_n_ao, lp_p_ao, VDD1V8BB, VSS1V8A, VSS1V8BB, VSS_SUB, bbmux_lp_n_ai, bbmux_lp_p_ai,
ibg_lp_untrim_50u_p_ai, iptat_lp_untrim_50u_p_ai, lp_en_i, lp_n_ai, lp_noise_filter_en_i,
lp_p_ai, lp_test_sel_i, trim_lp_fb_fc_i, trim_lp_pass_fc_i, vcm1_750m_ai, vcm3_600m_ai
);
timeunit 1ps;
timeprecision 1ps;
input analog_t VSS1V8BB;
input analog_t VSS1V8A;
input analog_t VSS_SUB;
input analog_t VDD1V8BB;
input signal_rf bbmux_lp_p_ai;
input signal_rf bbmux_lp_n_ai;
input signal_rf lp_p_ai;
input signal_rf lp_n_ai;
input analog_t vcm1_750m_ai;
input analog_t vcm3_600m_ai;
input analog_t ibg_lp_untrim_50u_p_ai [1:0];
input analog_t iptat_lp_untrim_50u_p_ai [1:0];
input logic lp_en_i;
input logic lp_noise_filter_en_i;
input logic lp_test_sel_i;
input logic [2:0] trim_lp_fb_fc_i;
input logic [3:0] trim_lp_pass_fc_i;
output analog_t lp_p_ao;
output analog_t lp_n_ao;
output analog_t lp2_p_amux_ao;
output analog_t lp2_n_amux_ao;
output analog_t lp1_p_amux_ao;
output analog_t lp1_n_amux_ao;
I still get the same error.
.bbmux_lp_n_ai(bbmux_lp_n_ai) ,
|
xmelab: *E,TYCMPAT (/var/vob/ctrx/ctrx44/vob/units/ctrx_tb_dig/source/sv/tb/abeam_wrapper_13/abeam_wrapper/rxbb_lp_model.sv,105|31): port or terminal connection type check failed on instance tb_rxbb_lp_model_wrapper.rxbb_lp_model_wrapper_inst (expecting datatype compatible with ‘unpacked structure rxbb_lp_model::signal_rf’ but found ‘unpacked structure $unit::signal_rf’ instead).
I have tried to both import and include my package. I also tried to write as a part of a module and include it, it does not work.
Any suggestions would be very helpful
Thank you