Writing task inside a function

SystemVerilog
,
1

As I know we cannot write tasks inside a function, so how can we write $display, $monitor inside functions. If we can then I want to know what is the difference between task and systemtask?

2

In reply to santosh_1004:

This is leftover terminology from Verilog where functions were required to have return values and arguments. Systemtasks should really be renamed System functions. See 0002027: calling system tasks from functions - Accellera Mantis

3

In reply to santosh_1004:

Hi,
We can write task inside function. Please find below code for the reference

module task_function;
function call();
begin
task_a();
end
endfunction

task task_a();
fork
#2 $display(“After 2 ns”);
#5 $display(“After 5 ns”);
join_none
endtask

initial
begin
call();
#20 $display(“after function call”);
end
endmodule

4

In reply to Arshia:

Hello Arshia,
I tried running your code in EDA Playground.
It showed…
ERROR VCP2802 “Function cannot enable a task.” “testbench.sv” 6 9
WARNING VCP2814 “Function call should return a value.” “testbench.sv” 4 15
WARNING VCP2803 “Function call result is ignored.” “testbench.sv” 19 7
FAILURE “Compile failure 1 Errors 2 Warnings Analysis time: 0[s].”

you can remove those warnings by specifying a return type but still functions can’t enable a Task.

5

In reply to santosh_1004:

Hi Santosh,

I guess due to simulator run.

I have used running the Synopsys Simulator and showing me the below result:

After 2 ns
After 5 ns
after function call
V C S S i m u l a t i o n R e p o r t
Time: 20 ns

Regards,
Arshia

6

In reply to Arshia:

SystemVerilog does not allow functions to have blocking statements, and explicitly;

A function shall not enable tasks regardless of whether those tasks contain time-controlling
statements.

This is a tool bug, If you used your function with a delay in an expression, it would not make any sense.

7

In reply to dave_59:

Thanks Dave for the confirmation!