Writing SVA sequence involving a bus

SystemVerilog
,
8

In reply to pavan yalamanchili:

How about adding the test for the fell in the loop?


    always @ (posedge clk) begin 
        static int i; 
        for(i=0; i <= 31; i++) begin 
          if($rose(my_bus[i])) rose_bus[i]<=1'b1;
          if (flag) ap_fell: assert(!$fell(my_bus[i])); 
        end
    end

I have issues with
(my_bus===0) |=> (!($fell(my_bus[i])[->1]) intersect q_all_rose);

  1. Too many not needed attempts when my_bus==0 for many cycles. That is why I had the “go” variable that fired once.
  2. !sequence is illegal
  3. (!$fell[i][->1] is not what you want


import uvm_pkg::*;
`include "uvm_macros.svh"
 
module allrose;
    bit [31:0] my_bus, rose_bus; 
    bit clk, go=1'b1, flag; 
    function void setgo(bit val, bit [31:0] val2, fg);
        go=val;
        flag=fg;
        rose_bus= val2;
    endfunction 
    
    initial forever #5 clk=!clk; 
    sequence q_all_rose; 
        $countones(rose_bus)==32 [->1]; 
    endsequence
    
    always @ (posedge clk) begin 
        static int i; 
        for(i=0; i <= 31; i++) begin 
          if($rose(my_bus[i])) rose_bus[i]<=1'b1;
          if (flag) ap_fell: assert(!$fell(my_bus[i])); 
        end
    end 
    
    ap_allrose: assert property(@(posedge clk) 
            go |-> (1, setgo(1'b0, 0, 1)) ##0 q_all_rose) setgo(1'b1, 0, 0); 
endmodule

Ben Cohen SystemVerilog.us