In reply to ben@SystemVerilog.us:
Does the following assertion satisfy the condition!
Checking for !($fell(my_bus[i])) on each bit until the numbers of 1’s in my_bus is 32
sequence q_all_rose;
$countones(rose_bus)==32 [->1];
endsequence
generate
for (genvar j = 0; j < 31; j = j + 1) begin
ap_allrose: assert property ( @(posedge clk)
(my_bus===0) |=> (!($fell(my_bus[i])[->1]) intersect q_all_rose);
end
endgenerate