Writing SVA sequence involving a bus

SystemVerilog
,
6

In reply to lanfranco.salinari:

How about having supporting logic to detect the rose, and do the $countones on that vector?



import uvm_pkg::*;
`include "uvm_macros.svh"
 
module allrose;
    bit [31:0] my_bus, rose_bus; 
    bit clk, go=1'b1; 
    function void setgo(bit val, bit [31:0] val2);
        go=val;
        rose_bus= val2;
    endfunction 
    
    initial forever #5 clk=!clk; 
    sequence q_all_rose; 
        $countones(rose_bus)==32 [->1]; 
    endsequence
    
    always @ (posedge clk) begin 
        static int i; 
        for(i=0; i <= 31; i++)
          if($rose(my_bus[i])) rose_bus[i]<=1'b1;
    end 
    
    ap_allrose: assert property(@(posedge clk) 
            go |-> (1, setgo(1'b0, 0)) ##0 q_all_rose) setgo(1'b1, 0); 
endmodule

Ben Cohen SystemVerilog.us