In reply to ben@SystemVerilog.us:
Yes, it is closer to my goal, but still does not fulfill the requirement that individual signals must only rise, not fall.
ap_allrose is successful even if the sequence is 00000000 → 00000001 → 00000000 → FFFFFFFF, where bit 0 toggles 3 times.
Maybe some condition on monotonicity of $countones(my_bus) could help, but it is not intuitive for me.
Best regards,
Lanfranco