Writing SVA sequence involving a bus

SystemVerilog
,
4

OK, I believe that the following may work for you. The key is this sequence that waits till
number of bits in ny_bus==32. I put the sequence into an assertion that once successfully attempted with go==1, go is disabled until success.
$countones(my_bus)==32 [->1];



import uvm_pkg::*;
`include "uvm_macros.svh"
 
module allrose;
    bit [31:0] my_bus; 
    bit clk, go=1'b1; 
    function void setgo(bit val);
        go=val;
    endfunction 
    
    initial forever #5 clk=!clk; 
    sequence q_all_rose; 
        $countones(my_bus)==32 [->1]; 
    endsequence
    
    ap_allrose: assert property(@(posedge clk) 
            go |-> (1, setgo(1'b0)) ##0 q_all_rose) setgo(1'b1); // else setgo(1'b1); 
    
    
endmodule

Ben Cohen http://www.systemverilog.us/

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