Writing into memory and reading from memory

SystemVerilog
, ,
6

In reply to basilleaf:

You do not have any delay statements within the write/read task.
This schedules both read and write operation at the same simulation cycle.
Hence the read task does not see the updated value of byte_data instead the initial value.

I added a $time to your display statements and see the below result:
Note: 0ns timestamp prints in the result.


  $display("At %0tns Value of address = %0h, data = %0h",$time, address,byte_data);    
  ...
  ...
  $display("At %0tns Value of address = %0h",$time, address); 
  $display("At %0tns Value of data = %0h",$time, byte_data);

Result:
At 0ns Value of address = 0000000012345678, data = 01
At 0ns Value of address = 0000000012345678
At 0ns Value of data = 00