Writing Assertions for FSM

SystemVerilog
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2

In reply to sai_pra99:
Your main issue here is that in the antecedent you are ANDing a logical variable (the “&”) with a sequence, and that is ILLEGAL. Specifically, you have


(p_wren && setup_state) // setup_state is declared as a sequence 
// Thus, the compiler sees 
sequenceA && sequenceB // p_wren is a sequence of 1 term. 
// If you really want the AND, then you need the sequence AND operator, which is "and".
// I would use the Sequence fusion (##0) operator, Thus, 
 
   sequence setup_state;
    (state==SETUP_PHASE);
  endsequence
  
  property stable_wr_data;
    disable iff(!p_rstn)
    @(posedge p_clk)
   // (p_wren && setup_state) |-> ##1 !($isunknown(tmp_data) && $isunknown(tmp_addr));
    (p_wren ##0 setup_state) |-> ##1 !($isunknown(tmp_data) && $isunknown(tmp_addr));
  endproperty

There are other things about your code that needs to corrected, from a style point of view.

  1. Don’t use a program, use a checker or a module
  2. You have way too many sequence declarations of 1 term, why not put them inline with your assertion or with your property.
  3. If a property is used once and does not have local variables, then put the property contents within the assertion.
 ap_stable_wr_data: assert property( // better style
disable iff(!p_rstn)
@(posedge p_clk)
// (p_wren && setup_state) |-> ##1 !($isunknown(tmp_data) && $isunknown(tmp_addr));
p_wren && state==SETUP_PHASE |-> ##1 !($isunknown(tmp_data) && $isunknown(tmp_addr)) );
  1. Use the SystemVerilog style for port list, instead of Verilog style.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

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