Hi,
we have a requirement which states that a derived clock should toggle after an enable signal is asserted. (clock should be low when enable is low). Also enable may be asserted asynchronously with reference to derived clock. Also the derived clock is a submultiple of main clock and division factor is set in a register.
I am not clear how to write the assertion since the clock ON and OFF time is a variable and we cannot use ##n delay construct since it requires the n value to be constant.
Also since enable signal is asserted asynchronously with reference to the clock, there can be a glitch in the clock.
Can someone explain how there requirements can be put in an assertion statement.
regards,
-sunil