Hi
I would like to know,if we can write a state machine code in our testbench using system verilog classes.
Please help me in architecting a state machine inside a class.
regards
RAJIV
I have done this. Basically, the fsm resides in a class method (task).
Thanks,
Babu
Rajiv,
A state machine is a very broad topic. In academic terms, any function of new inputs together with previous outputs can be made into a state machine. (I’m using function in the generic sense, both as an SV function or task). Somewhere you need to store the outputs, and you need to define when the function gets called. The only difference between using a class versus Verilog RTL to build a state machine is how you schedule the the timing of the call.
In typical Verilog RTL, an always block is used to create a process that repeats the code block every clock cycle. With classes, you can use fork/join_none to dynamically create a process. Hopefully, you are using the OVM or UVM which has a component that does this for you. If you look at the driver of any example here, you will almost always see a state machine in the implementation of the code.