Can anyone please solve this and reply me.
In reply to @jpk4pj:
Write the assertion to verify the read pointer & write pointer functionality of FIFO (16X8 FIFO).
Assertions are based on requirements.
Write the requirements, the assertions will fall-in naturally.
Requirements to consider:
- When does the read pointer increment?
- When does the write pointer increment?
- Can the read pointer be greater than the write pointer?
- When to flag error conditions?
In my SVA Handbook I provide a definition of the requirements for a synchronous FIFO used as IP, and I demonstrate by example how properties unambiguously clarify requirements. Here are a couple of property examples:
// never a push and full and no pop
property p_push_error;
@ (posedge clk)
not (push && full && !pop);
endproperty : p_push_error
ap_push_error : assert property (p_push_error);
// never a pop on empty
property p_pop_error;
@ (posedge clk)
not (pop && empty);
endproperty : p_pop_error
ap_pop_error : assert property (p_pop_error);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf