I have pasted my code below.
I have analysis_port instantiated in class and_driver and and_monitor from where I am calling write function (drv_to_scb.write(from and_driver) and to_scoreboard.write(from and_monitor)) .
In the Scoreboard, instead of using uvm_analysis_imp_*, I used uvm_analysis_export and connected it to and_predictor’s analysis_export.
And inside and_predictor, I have connected analysis_export to expfifo and outfifo as shown below.
I didn’t define the write function anywhere in and_predictor or even in and_scoreboard.
I am not using put function to write to uvm_tlm_analysis_fifo in the below mentioned code.
I am calling write function in and_monitor as well as in and_driver as shown below and I am seeing the data getting written to uvm_tlm_analysis_fifo. can this happen?
class and_driver extends uvm_driver#(packet);
virtual and_if vif;
packet g;
**uvm_analysis_port #(packet) drv_to_scb;**
`uvm_component_utils(and_driver)
function new (string name, uvm_component parent);
super.new(name,parent);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
drv_to_scb = new("drv_to_scb",this);
if(!and_vif_config::get(this,"","vif",vif))
`uvm_fatal("NOVIF",{"virtual interface is not defined. set it for:",get_full_name(),".vif"});
endfunction: build_phase
virtual task run_phase(uvm_phase phase);
fork
get_and_drive();
join
endtask: run_phase
virtual task get_and_drive();
forever begin
seq_item_port.get_next_item(req);
$display("writing to scoreboard");
**drv_to_scb.write(req);**
$cast(g,req.clone());
drive_pins(g);
seq_item_port.item_done();
end
endtask : get_and_drive
virtual task drive_pins(packet trans);
begin
vif.a = trans.a;
vif.b = trans.b;
vif.c = trans.c;
#25;
end
endtask : drive_pins
endclass : and_driver
class and_monitor extends uvm_monitor;
`uvm_component_utils(and_monitor)
**uvm_analysis_port #(packet) to_scoreboard;**
virtual and_if vif;
packet pkt;
function new (string name, uvm_component parent);
super.new(name,parent);
to_scoreboard = new("to_scoreboard",this);
pkt = new();
endfunction : new
function void build_phase(uvm_phase phase);
virtual and_if aif;
super.build_phase(phase);
if(!and_vif_config::get(this,"","vif",aif))
`uvm_fatal("NOVIF",{"virtual interface is not defined. set it for:",get_full_name(),".vif"});
$display("vif assigned");
vif = aif;
endfunction: build_phase
task run_phase(uvm_phase phase);
fork
forever @(vif.a or vif.b or vif.c or vif.d or vif.d or vif.e or vif.f or vif.y or vif.z)
begin
#3;
pkt.a = vif.a;
pkt.b = vif.b;
pkt.c = vif.c;
pkt.d = vif.d;
pkt.e = vif.e;
pkt.f = vif.f;
pkt.y = vif.y;
pkt.z = vif.z;
$display("to_scoreboard write called",$time);
**to_scoreboard.write(pkt);**
end
join
endtask
endclass : and_monitor
class and_scoreboard extends uvm_scoreboard;
`uvm_component_utils(and_scoreboard)
packet pkt1;
packet pkt2;
and_predictor abcd;
**uvm_analysis_export #(packet) m_imp_mon;
uvm_analysis_export #(packet) m_imp_drv;**
function new(string name, uvm_component parent);
super.new(name,parent);
m_imp_mon = new("m_imp_mon",this);
m_imp_drv = new("m_imp_drv",this);
abcd = new("abcd",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
**m_imp_drv.connect(abcd.m_imp_drv_pred);
m_imp_mon.connect(abcd.m_imp_mon_pred);**
endfunction
task run_phase(uvm_phase phase);
endtask
endclass
class and_predictor extends uvm_component;
`uvm_component_utils(and_predictor)
uvm_analysis_export #(packet) m_imp_mon_pred;
uvm_analysis_export #(packet) m_imp_drv_pred;
uvm_tlm_analysis_fifo #(packet) expfifo;
uvm_tlm_analysis_fifo #(packet) outfifo;
packet pkt1;
packet pkt2;
function new(string name, uvm_component parent);
super.new(name,parent);
expfifo = new("expfifo",this);
outfifo = new("outfifo",this);
pkt1 = new("pkt1");
pkt2 = new("pkt2");
m_imp_mon_pred = new("m_imp_mon_pred",this);
m_imp_drv_pred = new("m_imp_drv_pred",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
**m_imp_drv_pred.connect(expfifo.analysis_export);
m_imp_mon_pred.connect(outfifo.analysis_export);**
endfunction
task run_phase(uvm_phase phase);
packet exp_pkt,act_pkt;
forever begin
expfifo.get(exp_pkt);
outfifo.get(act_pkt);
exp_pkt.y = (exp_pkt.a && exp_pkt.b && exp_pkt.c);
if((act_pkt.y != exp_pkt.y)) begin
$display("predictor act_pkt.y is %d",act_pkt.y);
$display("pred act_pkt.z is %d",act_pkt.z);
$display("pred exp_pkt.y is %d",exp_pkt.y);
$display("pred exp_pkt.z is %d",exp_pkt.z);
`uvm_error(get_type_name(),"Dayalan Comparison FAIL");
end else begin
$display("pred act_pkt.y is %d",act_pkt.y);
$display("pred act_pkt.z is %d",act_pkt.z);
$display("pred exp_pkt.y is %d",exp_pkt.y);
$display("pred exp_pkt.z is %d",exp_pkt.z);
`uvm_info(get_type_name(),"Dayalan Comparison PASS",UVM_NONE);
end
end
endtask
endclass