Write an assertion ,after the clk has arrived within 5 clk cycles write or read should not occur

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben ,
I executed the above code

assert property (not(read || write))

in edaplayground it is showing below error
Error-[PAOCNAILS] Procedural assertion in a loop
Procedural assertion ( i.e., assert, assume or cover property) is not allowed in looping statement.Only immediate assertions are allowed in this context.