Write an assertion ,after the clk has arrived within 5 clk cycles write or read should not occur

SystemVerilog
, , ,
4

In reply to SUNODH:
You can use the current assertion with the not(property).
An imediate asserion uses expressions and does not use properties.


initial
    begin
    repeat(10)
      begin
        @(posedge clk)
        // That clocking event flows into the property 
        ap_rdwr_init: assert property (not(read || write))
          $display ($time, " PASS:: write = %0d, read = %0d   |  @_Time = %0t\n", $sampled(write),$sampled(read),$time);
        else
          $fatal ($time, " FAIL:: write = %0d, read = %0d   |  @_Time = %0t\n", $sampled(write),$sampled(read),$time); 
      end
    end

On first_match (not_read_write), You need to study what first_match of a sequence means,
and ask yourself what the first_match of a expression results into.
Ben