Write a constraint for this scenario

SystemVerilog
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1
  1. take a dynamic array and array size should be 10.
  2. For 1st halfcycle the all memory locations should be zero and 2nd halfcycle the all memory locations should be one.
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In reply to surya narayana Gutha:

There is nothing random about this. Why do you need a constraint? And what is a “halfcycle”?

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In reply to dave_59:

Hi dave,
Here halfcycle means with respect to clock , In that 1st positive clock cycle I would like to print all zeros in all locations and similarly 1st negative clock cycle print 0ne’s in all locations.

I tried with distribution constraint,but some how it is not working.

Thanks & Regards,
Surya

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In reply to surya narayana Gutha:

Can you show us the code you tried as an example. SO that it is easier to see why it did not work