Working of randcase

SystemVerilog
, ,
1

Hi,
I was trying the following code where the intent is to read tables randomly

 bit[4:0] ct , qt , ht , nt , et; // Provision for diff. weights for respective table read

 initial begin
 // By default all tables have equal weight
   ct = 1;
   qt = 1;
   ht = 1;
   et = 1;
   nt = 1;
  // Using run-time switches user can change the weights below
   .........

  randcase 
    ct: begin
             rd_ct();
          end
    qt: begin
             rd_qt();
          end
    ht: begin
            rd_ht();
          end
    et: begin
            rd_et();
          end
    nt: begin
            rd_nt();
          end
  endcase

end

LRM 18.16 mentions ::

Each call to randcase retrieves one random number in the range of 0 to the sum of the weights. The
weights are then selected in declaration order: smaller random numbers correspond to the first (top) weight statements.

Assume that there is no provision for run-time switches i.e all weights are equal to 1,
how does the above LRM quote apply ?

Sum of weights would be 5 however I am not clear on “weights are then selected in declaration order: smaller random numbers correspond to the first (top) weight statements.”

2

The section you quoted from the LRM is incorrect and unnecessary. It should be in the range zero to the sum of the weights minus one. The branch chosen is the last branch where the sum of all the accumulated weights is less than the retrieved random number.

Any case this is an implementation detail and should be removed from the LRM. All you need to know is how the probabilities are calculated from the weights.

https://accellera.mantishub.io/view.php?id=8483