In reply to ben@SystemVerilog.us:
Ben I am not sure if I get your comment .
Do you mean this way ::
always @( negedge rst_n , posedge clk )
begin
if ( ! rst_n ) begin
assert ( ! rsn ) $display($time,,,"...") ; // Immediate assertion .
// Drive initial values to signals
end
else
begin
// Non - Reset Logic here
.............................
end
end
I was looking for a way in concurrent assertion written outside procedural block. Like in the example at the top .