Will the assertion trigger if my clock is Unknown

SystemVerilog
, ,
3

In reply to ben@SystemVerilog.us:

I tried the below code on EDA and it triggers the assertions. So wanted to double check

module GRG_assert2;

  logic clock;
  logic a, b, c, d;
  
  assign #5 clock = x;
  
  initial begin
    
    $asserton;
    repeat (30) @(posedge clock)
      void'(std::randomize(a, b, c)  ); 

    $stop;    
    
  end

  assert property (@(posedge clock) a |-> b |-> c) 
    $display("implication property passed with a=%b, b=%b, c=%b, clk=%b",
             $sampled(a), $sampled(b), $sampled(c), $sampled(clock));
    else
      $display("implication property failed with a=%b, b=%b, c=%b, clk=%b",
               $sampled(a), $sampled(b), $sampled(c), $sampled(clock));

endmodule