Will the assertion trigger if my clock is Unknown

In reply to sj1992:
Try it!
However, if clk==1’bX, the @(posedge clk) produces NO event, thus will not assertion will not trigger.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  1. VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
  2. http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
  3. “Using SVA for scoreboarding and TB designs”
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  4. “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
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  5. SVA in a UVM Class-based Environment
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