Will always_comb block trigger if the signal value changes from 0/1 to X

SystemVerilog
, , ,
5

In reply to dave_59:

Hi Dave,

The Signal is inside the DUT RTL and is getting assigned in an always block. But when this signal gets assigned the value X in RTL I want to make it to 0. So I am trying to use force and release in my testbench so that the signal never becomes X. But this force and release dont seem to work.

Thanks