Will Always block triggers when strength of signal changes? or it will only trigger when face value(0,1,x,z) will change?

SystemVerilog
1

Hi,

Below is the always block which will be triggered when value of a changes .
My Question is Will always block be triggered when only strength of signal ‘a’ changes ?
Below is the snippet to support my question ?

inout a;
logic out;
logic s;

assign (pull1,pull0) a = s;

always@(a)
begin
out = a;
end

2

In reply to Harjot:

Yes, strength is part of the value of a net. A few more lines of code in your example would have demonstrated this behavior.

module top;
  wire a;
  logic out, s,r='z;
  assign (pull1,pull0) a = s;
  assign a = r;

  always@(a)begin
    out = a; $display ("%t a changed %v", $time, a);
  end
  
  initial begin
    #1 s = 0;
    #1 r = 0;
    #1;
  end
  
endmodule
3

Hello dave,
Can you please explain how assigning the actual value to a local wire ignores strength changes and only considers value changes?
module top;
wire a, b ;
logic out, s,r='z;
assign (pull1,pull0) a = s;
assign a = r;
assign b = a;

always@ (b) begin
out = a; $display (“%t a changed %v”, $time, a);
end

initial begin
#1 s = 0;
#1 r = 0;
#1;
end

endmodule
Thanks