Why we are not using enum handles at the outside of the class to access any enum value while using ::(scope resolution)

SystemVerilog
1

In System Verilog:

for ex:-

class A;

typedef enum logic [1:0] {RESET, WAITE, LOAD, READY} states_t;
…
…
endclass

why we are not using enum handle to access enum value of ‘RESET’ from outside of the class by using ::(scope resolution)

i.e A::RESET;
why can’t A::St::RESET (Assume we are creating handle to enum data type i.e states_t St)

2

The correct syntax to reference an enum label is A::RESET. The labels are at the same scope level as the typename. That is why you are not allowed to use the same enum label in different enums within the same scope.