Why uvm_root is singleton in UVM? what is the difference between static and singleton class?

UVM
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1

Why uvm_root class in UVM library is defined as singleton class?
Why can’t we use static in place of singleton?
What is the difference between static class and singleton class?

2

In reply to Sagar Shah:
There are no static classes in SystemVerilog. All class objects are constructed dynamically at runtime. You can have static class variables. The singleton pattern ensures that only one class object of the type uvm_root ever gets constructed.

3

In reply to dave_59:

Thanks Dave.