Why uvm_hdl_force can not force a logic output

SystemVerilog
1

hi,
I encountered an issue with uvm_hdl_force usage. I tried to use uvm_hdl_force to force an output logic signal of a module, but it didn’t appear to be successful based on the waveform. However, when I use +fsdb+force run-option, the force points shown on the waveform indicate that it was successful, but the signal value was not forced to the expected value. I would like to know why this is happening and if there are any limitations to using uvm_hdl_force.
The simplified code is as follows. In the actual project, ‘b’ is the output of some internal module, and I am using force in the testcase.


module top
  input logic a;
  output logic b;
endmodule
module test_top;
  initial begin
    uvm_hdl_force("top.b", 1);
  end
endmodule
2

In reply to jianfeng.he:

Using uvm_hdl_force requires tool specific options to preserve the signal you want to force.

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