Why UVM has 2 implementaion ports for uvm_analysis_port?

UVM
1

Hi Experts,

For uvm_blocking_put_port#(T) the export is uvm_blocking_put_imp#(T)
Similarly for uvm_blocking_get_port the export is uvm_blocking_get_imp#(T)

But for the

uvm_analysis_port

we have

Why we have 2 implementation port ?

Regards,
Georgean

2

Hi,

There is a difference between uvm_analysis_export and uvm_analysis_imp.

uvm_analysis_imp is the actual implementation port, which calls the write function of the component which instantiates it.

uvm_analysis_export is used to export the port connection to all its connected implementations and subsequently to their instantiating component’s write functions. i.e., the write function of uvm_analysis_export calls the write functions of all the connected interfaces (which can be exports / imp’s), whereas the write function of uvm_analysis_imp calls the write function in component.

With reference to the uvm_blocking_put/get_port, in addition to uvm_blocking_put/get_imp, there is also uvm_blocking_put/get_export. And these exports are to be ultimately terminated in an implementation port, which calls its instantiating component’s put/get() tasks.

Long answer short, there are exports and implementation ports for blocking_put/get_port, similarly, there are exports and implementation ports for analysis_port as well.

-Sailaja.

3

In reply to Sailaja:

Thank you.