Why this is not possible to assign base_class to child_class ? and why do we need $cast() to assign base_class to child_class?

SystemVerilog
,
1

// what is the reason behind this we can not assign parent_class handle to child_class handle ?

class base_class;
endclass

class child_class extends base_class;
endclass

module top;
base_class bc;
child_class cc;
initial
begin
bc = new();
cc = new();

cc = bc; // assigning base_class handle to child class || why this is not possible to do like this ?
end
endmodule

2

In reply to gautammallick92:

See use of $cast | Verification Academy

and OOPS terminologies in SV | Verification Academy