In reply to designMaster:
The fatal is caused by a timeout:
UVM_FATAL /playground_lib/uvm-1.2/src/base/uvm_phase.svh(1491) @ 9200000000000: reporter [PH_TIMEOUT] Default timeout of 9200000000000 hit, indicating a probable testbench issue
As I said this timeout appears because of the missing driver. Your sequencer generates 1 transaction. But this transaction is not processed by the driver. The sequencer is waiting. The timeout stops the simulation.