Why the configuration performed in test override the one done in env

UVM
,
1

Hi,
This is related to uvm_1.1 example intergrated/ubus/
In class test_2m_4s (in file test_lib.sv), the ubus_example_tb0.ubus0.num_masters is set to 2 with following code:
uvm_config_db#(int)::set(this, “ubus_example_tb0.ubus0”, “num_masters”, 2);

In class ubus_example_tb (in file ubus_example_tb.sv), the ubus0.num_master is set to 1 with following code:
uvm_config_db#(int)::set(this, “ubus0”, “num_masters”,1);

Because the testbench is built top-down, I expect that the num_master value 1 set by class ubus_example_tb should override 2 which is set by test_2m_4s, which is sitting in upper level.
However, the simulation shows that the final value of num_masters is 2.
Can anyone explain why?

Thanks in advance and best regards,
Xun

2

The uvm_config_db takes into account the hierarchical precedence with respect to the configuration settings. In this example, since the test_2m_4s instantiates the ubus_example_tb, any uvm_config_db settings done in the test will override the settings done in the ubus_example_tb.

This is done to allow tests to control the configuration of the environment.

3

Hi cgales,
Thank you very much!
I found the same explanation in UVM_1.1_Class_Reference.
“… the cntxt hierarchy is used to determine the setting’s precedence in the database.
Settings from hierarchically higher levels have higher precedence. Settings from the same level of hierarchy have a last setting wins semantic.”

Best Regards,
Xun