Hi there, I got a piece of SVA code with testbench, but it failed out of my expectation.
Would anyone can help me with this?
module disableiff_assertion(
input wire clk,a,b,valid,
output reg result);
always@(posedge clk) begin
if(valid) begin
result <= a & b;
end
else result <= 0;
end
property andc;
@(posedge clk)
disable iff(!valid)
result == (a & b);
endproperty
assert property(andc);
endmodule
//+++++++++++++++++++++++++++++++++++++++++++++++
module tb();
reg clk = 0,valid, a, b;
wire result;
always #5 clk ++;
initial begin
a = 0; b = 0;
valid = 0;
#30 valid = 1;
#40;
#5 a = 1; b = 1;
#5 a = 0;
#10 a = 1;
#10 b = 0;
#10 b = 1;
#100 $finish;
end
disableiff_assertion dut (clk,a,b,valid,result);
endmodule