Why results differs w/ and w/o declaring virtual methods in extended class

SystemVerilog
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2

In reply to tsb_matumoto:

The reason for this is that you have defined A and B in your base and extended classes. This is rather tricky and not a recommended practice. In this case an object from the extended class will have “A”, “B”, “super.A”, “super.B”. A method in the base class, virtual or not, that is not overridden will access variables in the base class, they cannot access variables in the derived class. So “P1.printA” will access “super.A” which has a value of “1”. While “P1.printB” since it was overridden, will access “B” which has a value of “4”.

So as a remedy, remove duplicate definitions of properties in the extended class.


class My_Packet extends BasePacket;
  //int     A; //--COMMENT OUT--
  //int     B; //--COMMENT OUT--