Why isn't a race condition occurring here?

SystemVerilog
, ,
1

I have the following piece of code to swap two numbers:

class Example;
  
  function void swap(int x, int y);
    int temp;
    $display("Before swap: x = %0d, y = %0d", x, y);
    temp = x;
    x = y;
    y = temp;
    $display("After swap: x = %0d, y = %0d", x, y);   
  endfunction
  
  
  
endclass

module TB;
  initial begin
    Example E;
  
    E = new();
    fork  begin
      E.swap(20, 150);      
      E.swap(11, 22);
      E.swap(55, 44);
      E.swap(0,0);
    end
        
    join  
  end  
  
endmodule

I expected a race condition here for the swaps (inside the fork…join) because I have NOT defined the function to be “automatic” but the result looks fine (swaps are correct!). Why is that?

I made the “swap” function automatic and swaps are correct there too.

Confused :( Any insight is greatly appreciated.

2

In reply to Verif Engg:

Functions and tasks in classes are by default automatic.
1800, page 128Class methods (see Clause 8) and declared for loop variables (see 12.7.1 ) are by default automatic, regardless of the lifetime attribute of the scope in which they are declared.

Automatic variables and elements of dynamically sized array variables shall not be written with nonblocking, continuous, or procedural continuous assignments. Non-static class properties shall not be written with continuous or procedural continuous assignments. References to automatic variables and elements or members of dynamic variables shall be limited to procedural blocks.

1800, page 174 The lifetime of methods declared as part of a class type shall be automatic. It shall be illegal to declare a class method with a static lifetime.

Ben