Why is uvm_reg_filed always random value as like "rand uvm_reg_field"?

UVM
1

Hi,

I am studying uvm register layer and observed several times that uvm_reg_field is used as random variable on the customer site.
I don’t have much understanding for uvm register layer, so I wonder why it is always random variable.
I’ve tried to find the answer on web and uvm user guide, but I didn’t find.

Is there anyone who can explain why?

Thanks
Sungjin

2

In reply to supark:

It is upto you.
If you want to randomize those fields then you can declare as rand if not it is also ok.
However, important is you can randomized those fields only if you set is_rand = 1 in configuration method.


  // Reference uvm_reg_field.svh. 
  791  function void uvm_reg_field::configure(uvm_reg        parent,
  792                                        int unsigned   size,
  793                                        int unsigned   lsb_pos,
  794                                        string         access,
  795                                        bit            volatile,
  796                                        uvm_reg_data_t reset,
  797                                        bit            has_reset,
  798                                        bit            is_rand,
  799                                        bit            individually_accessible); 
  .......
  .......
  842    if (!is_rand)
  843      value.rand_mode(0);

Most of times RAL model is generated by automatically via tool/script.
So, tool/script you were using might considering rand always at declaration time and control of randomization enable or not via is_rand at configuration time.

Thanks!