In reply to ben@SystemVerilog.us:
Making the task NOT automatic and usi G nonblocking assignments works.
.
// Code your testbench here
// or browse Examples
// Code your testbench here
// or browse Examples
module tb;
bit clk;
initial forever #10 clk=!clk;
task my_first_task ();
// @(posedge clk);
data <= 8'h2; // non-blocking assignment may not be an automatic variable
for (int i=0; i <1; i++) begin
$display ("@ %t Entering the loop ", $realtime);
end
for (int i=0; i <1; i++) begin
$display ("Entering the second loop");
end
endtask
logic [31:0] addr, data;
initial begin
data = 'h10;
addr = 'h01;
fork
begin
// @(posedge clk);
@ (data);
$display ("@ %t Read from bus %h \n", $realtime, data);
end
my_first_task ();
join
end
endmodule
KERNEL: @ 0 Entering the loop