Why is the @data not triggered on a value change?

SystemVerilog
9

In reply to rag123:

See https://verificationacademy.com/forums/systemverilog/driving-wire-task-interface.
On using nonblocking assignment in tasks
Driving a wire thru a task is illegal.
Quote:
1800-2012 14.3 Clocking block declaration

  • A clockvar whose clocking_direction is inout shall behave as if it were two clockvars, one input and one output, having the same name and the same clocking_signal.
  • Reading the value of such an inout clockvar shall be equivalent to reading the corresponding input clockvar.
  • Writing to such an inout clockvar shall be equivalent to writing to the corresponding output clockvar.

interface dut_mem_if (input logic clk);
	wire[31:0] data;  // <------------------- the bi-direct
 
	clocking driver_cb @ (posedge clk);
		inout data;   // <------------------- the bi-direct 
	endclocking : driver_cb
endinterface : dut_mem_if 
 
class dut_mem_driver; 
	virtual interface dut_mem_if.drvr_if_mp  vif;
 // ...
	virtual task write_task(logic [31:0] data, address);
		this.vif.driver_cb.data <= data;