Why I get an error when I connect an "interface port" of a module to an interface instantiation hierarchically when the hierarchy has a generate or vector instance?

SystemVerilog
,
1

Hello,

I am getting an error when I am try to create the following scenario.

interface intf ();
logic x;
endinterface

module top ();
for (genvar i=0; i<2; i++) begin : _top1_
top1 top1();
end
endmodule 

module top1 ();
top2 top2();
top3 top3();
endmodule

module top2();
intf intf1();
top2a top2a(.intf(intf1));
endmodule

module top3();
top3a top3a (.intf(top2.intf1));
endmodule

I get the following error
Illegal interface port connection through a generate or array instance.

Can somebody please explain, what is the reason for such a restriction.
Thanks.

2

In reply to gagan06:

I don’t get that error. Where are definitions for top2a and top3a?