Why i am seeing assertion fail msg even when i have used implication operator for every clk.?

SystemVerilog
, ,
3

In reply to dave_59:

In below example i am expecting when wr_en is high for 16 consecutive cycle then only full is going to be checked and if full is not high then only it should give a asssertion error not on every clk when it’s checking

//full_signal
sequence fifo_full;

( WR_EN )[*16] ;

endsequence

property full_prop;
@(posedge WR_CLK )
disable iff(!clear)
fifo_full |-> FULL;

endproperty

full_check : assert property(full_prop)
$info("[%0t] FULL_Property :::ASSERTED <<<<--------------------------------------------------------------------------------- “,$time);
else
$warning(”[%0t] WARNING FULL_Property ::: NOT ASSERTED ",$time);