Why downcasting is not allowed in SystemVerilog?

SystemVerilog
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3

In reply to dave_59:

Thanks Dave.

In above link you have mentioned that,
It is always legal to assign a derived class object handle to a base class variable because Derived class object inherited everything defined by the base class type. There is nothing you can’t reference from the base class variable.

Now refer below code, In below code after assigning derived class object handle to a base class variable I can’t access/reference member which is defined in Derived class (here int unsigned d) but still we can cast it, and we can’t cast reverse, why?

class base;
  int unsigned b;
endclass : base

class derived extends base;
  int unsigned d;
endclass : derived

module top();
  base B;
  derived D;

  initial begin
    D = new();
    D.b = 'hB;
    D.d = 'hD;
    if ($cast(B, D)) begin
      $display ("B.b:%0h", B.b);
      $display ("B.d:%0h", B.d);
    end
  end
endmodule : top

//Output:
//Error-[MFNF] Member not found
//"B."
//  Could not find member 'd' in class 'base', at "top.sv", 1.