Why doesn't it update?

SystemVerilog
, , ,
8

In reply to MarkLand:

I don’t understand why you are trying to make things more complex than necessary. Instead of trying to simulate a function call, why don’t you use an actual function call? Modules are designed for time-based hardware constructs. Functions are for zero time processing, just like in C.



function void sub(int toto);
  automatic int ml = 0;
  automatic int fou = 0;
  automatic int kol = 0;
  automatic int count = 0;

      begin
        case (toto)
          3: 
                begin
                  ml++;
                  fou = 54;
                  $display("hh %d %d",fou,count);
                  $display("out of 3 case");
                end
          5: 
                begin
                  kol++;
                  fou = 89;
                  $display("polo %d %d",fou,count);
                  $display("out of 5 case");
                end
          default: 
            begin
              count++;
              $display("default case %d",toto);
              $display("out of default case %d fin",toto,$time);
            end
        endcase
      end
endfunction
 
module main();
 
  int ki = 0;

  initial 
    begin
      #5 ki = 4;
      sub(ki);
      #5 ki = 3;
      sub(ki);
      #5 ki = 5;
      sub(ki);
      $display("FINISH");
    end
 
endmodule