In reply to MarkLand:
The example you are looking at is atypical from the way most RTL is written today. Most state machines (FSMs) execute with a synchronous clock; advancing to the next state every clock cycle.
The code in the Tiempo CPU is asynchronous. It does not get into an infinite loop because there are calls to tasks like read and write that wait for other events.
I don’t think this is a good example for someone just learning SystemVerilog.