In reply to MarkLand:
What results are you seeing? What results do you expect to see?
Just by looking at your code, I’m going to guess that you are experiencing an infinite loop in your initial-forever block. SystemVerilog will execute the forever loop in 0 time until there is a blocking event which allows time to advance. Without this, you will never get past time 0.
In your sub-module, you want to have an always @(ki) so that your module will react to changes in ki.