In reply to mallick1:
Your initial statement was “drive a module wire from within a task”
Can’t do that from a task.
You clarified by stating “legally driveable, i.e. needs to be an input wire or NOT a wire.” What about driving an inout port of a module when the state is in the input mode?
Again, you can’t do that from within a task, regardless of where the task is (i.e., in a module or a class instance).
SystemVerilog interface do have wires too.
Ben Cohen SystemVerilog.us