In reply to ben@SystemVerilog.us:
Thanks Ben for your input.
The example you are showing has got to do with continuous assign contention and that is true.
If 2 continuous assigns drive the same net, it will go to x in a hurry.
The question asked here has got to do with the question virtual interface existance in the language, at least that is what I am trying to answer.
The port being driven in my example dut.signal, whether driven via a virtual interface or a member of a modport, through a dotted reference, needs to be legally driveable, i.e. needs to be an input wire or NOT a wire.
Soummya